With an increase in traffic of Internet Protocol (IP) packets of these days, high-speed and large-capacity communication has been indispensable. Therefore, network equipments for supporting backbone networks have been demanded to improve packet processing capabilities as well as memories used in these network equipments have been demanded to realize a high-speed operation and a large-capacity.
In these circumstances, a DDR memory having a function referred to as Double Date Rate (DDR) has appeared and attracted attention, which is a high-speed synchronous Static Random Access Memory (SRAM) capable of high-speed operation exceeding 200 MHz.
FIG. 9 illustrates a data transfer rate difference between a conventional memory and a DDR memory. The conventional memory usually reads and writes one data at either the rising or falling edge of a clock signal, whereas the DDR memory is able to read and write data at both of the rising and falling edges of a clock signal (is able to process two word data in one clock cycle). That is, the DDR memory is able to realize a transfer rate which is twice that of the conventional memory (in addition, a Quad Date Rate (QDR) memory whose DDR function is expanded is a memory device having independently operable two input/output ports and capable of processing four word data every clock cycle.
With the progress of higher-speed CPUs, a memory bandwidth (date rate) has become a bottleneck in systems. However, when using the DDR memory having a wide bandwidth, the bottleneck can be removed, thereby enabling building of a high-speed network system. On the other hand, since an access time of the DDR memory is reduced to half of a normal data access time, a timing margin inevitably becomes tight, and this requires a memory access control to sufficiently use a performance of the DDR memory.
A conventional memory access control method uses a technology of controlling writing to and reading from a buffer to absorb a difference between an access unit of a supply memory and that of a storage memory, thereby fast transferring data having an arbitrary length from the supply memory to the storage memory ((see Japanese Laid-open Patent Publication No. 10-222460 (paragraph numbers [0014] to [0029], and FIG. 1)).
FIG. 10 is a block diagram of a conventional memory access controller using a DDR memory. A memory access controller 50 includes a DDR memory 51, an information RAM 52, a read controller 53, a FiFo 54, a delay compensator 55, and a packet assembly unit 56.
The DDR memory 51 stores a packet. The DDR memory 51 parallel-outputs, during reading of data (packet data) d1, the data d1 and a clock ck1 synchronized with the data d1 (a function of parallel-outputting read data and a clock is one of characteristics of the DDR function).
The information RAM 52 stores an address (a read start address) of the DDR memory 51, in which head data of the packet stored in the DDR memory 51 is stored. The read controller 53 receives a read start address and packet length information (length information of one packet), generates an address necessary for reading one packet, and outputs the generated address to the DDR memory 51.
The FiFo 54 receives, at its writing side, the data d1 and clock ck1 parallel-output from the DDR memory 51, and writes the data d1 using the clock ck1. The FiFo 54 outputs, at its reading side, data (hereinafter referred to as data d2) using a system clock ck2, and further generates phase difference information which is differential information between a phase of the previously output (n−1)th packet and a phase of the next output nth packet.
The delay compensator 55 receives the data d2 and phase difference information output from the FiFo 54, and compensates for a delay value (latency) caused by a clock transfer process. The packet assembly unit 56 receives the data output from the delay compensator 55, and detects head data of the packet from the received data. Then, the packet assembly unit 56 extracts the packet length information from the detected head data, notifies the read controller 53 of the packet length information, and arrays the data. Thus, the packet assembly unit 56 reassembles the packet. Thereafter, the packet assembly unit 56 outputs the reassembled packet to a downstream processor.
Here, operations of the read controller 53 will be described in detail below. When receiving the read start address stored in the information RAM 52, the read controller 53 recognizes, based on packet information (packet length information set in the head data actually read from the DDR memory 51) output from the delay compensator 55, a read end address indicating the end of the reading operation beginning at the read start address.
Then, the read controller 53 sequentially increments an address value beginning at the read start address value and ending at the read end address value to generate addresses corresponding to one pocket. Thereafter, the read controller 53 sequentially transmits the incremented address value to the DDR memory 51 and reads the data d1 corresponding to one packet from the DDR memory 51.
FIG. 11 is a block diagram of the delay compensator 55. The delay compensator 55 includes a shift register 51a, a selector 51b, and a timing generator 51c. Latches (FF) 51a-1 to 51a-n within the shift register 51a are cascade connected such that the output terminals of the latches are respectively connected to the input terminals of the selector 51b. The timing generator 51c generates a selection signal based on phase difference information and a packet read start signal output from the read controller 53, and transmits the selection signal to the selector 51b. 
Here, when the data d2 from the FiFo 54 is input to the shift register 51a, the data sets shifted by one clock cycle are output from the respective latches and input to the selector 51b. 
The selector 51b selects data at a desired timing based on the phase difference information (selection signal) from among a plurality of data sets output from the shift register 51a, and outputs the selected data as the delay-adjusted data. Since the switching of data selection by the selector 51b is performed in units of packets, the timing generator 51c performs a logical operation between the phase difference information and the packet read start signal, and generates a selection signal.
FIGS. 12 to 14 are schematic diagrams for illustrating a timing at which the delay compensation is performed. Stuff bits corresponding to one or more clocks are inserted between packets, thereby performing the phase adjustment (delay adjustment) using increase and decrease of the stuff bits. The data from the latch 51a-2 at the Xth stage in the diagram of FIG. 11 is used as the currently selected data.
The schematic diagram of FIG. 12 will be described. When no phase difference is present between a phase of the (n−1)th packet and that of the nth packet, the delay value remains unchanged as compared with the previous state. Therefore, the currently selected data output from the latch 51a-2 at the Xth stage is continuously output from the selector 51b. 
The schematic diagram of FIG. 13 will be described. When a phase of the nth packet is shortened by one clock as compared with that of the (n−1)th packet, it means that the delay value is reduced by one clock as compared with the previous state. Therefore, the selector 51b switches the latch from the current latch 51a-2 at the Xth stage to the latch 51a-1 at the X−1th stage, and selects the data output from the latch 51a-1 at the X−1th stage (stuff bits corresponding to one clock are lost but data loss of the packet itself is prevented).
The schematic diagram of FIG. 14 will be described. When a phase of the nth packet is lengthened by one clock as compared with that of the (n−1)th packet, it means that the delay value is increased by one clock as compared with the previous state. Therefore, the selector 51b switches the latch from the current latch 51a-2 at the Xth stage to the latch 51a-3 at the X+1th stage, and selects the data output from the latch 51a-3 at the X+1th stage (stuff bits corresponding to one clock are inserted). Although not shown in FIGS. 12 to 14, the delay corrector 55 generates and outputs enable signals indicating head data of the corresponding packet in addition to the delay-compensated packet data.
As described above, the delay corrector 55 performs delay compensation of the data d2 output from the FiFo 54. Further, the packet assembly unit 56 receives the delay-compensated packet data and the enable signals indicating head data of the packet. This structure makes it possible to accurately detect head data of each packet and to extract the packet length information from the head data.
However, the above-described structure of the conventional memory access controller 50 has the following problems.    (1) The delay value of read data from the DDR memory 51, which is caused by the clock transfer process, is irregular. Therefore, a complex mechanism (more specifically, the above-described delay compensator 55) for adjusting the delay value is required.    (2) For example, when the reading from the DDR memory 51 is completed before the read controller 53 receives the packet length information, the read controller 53 is unable to recognize the read completion because of receiving no packet length information, and therefore, fails to read the next packet from the DDR memory 51. This causes the read controller 53 to have a blank before receiving the packet length information. As a result, a data bandwidth is reduced to cause reduction in communication speed.    (3) The delay value also affects a wiring design on a printed circuit board where the memory access controller 50 is mounted. This makes it difficult to grasp an accurate delay value.    (4) The read controller 53 has a structure depending on the delay compensator 55 which performs the delay compensation, and therefore, is unable to independently perform the processing.